The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET).
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET, a small amount of voltage is applied to the gate (G) in order to control current flowing between the source (S) and drain (D). In FETs, the main current appears in a conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel current can be altered by varying the voltage applied to the gate terminal or by widening or narrowing the conducting channel and thereby controlling the current flowing between the source and the drain.
FIG. 1 illustrates a FET 100 comprising a p-type substrate (or a p-well in the substrate), and two spaced-apart n-type diffusion areas—one of which may serve as the “source”, the other of which may serve as the “drain” of the transistor. The space between the two diffusion areas is called the “channel”. The channel is where current flows, between the source (S) and the drain (D). A schematic symbol for an n-channel MOSFET (or NFET) appears to the left of FIG. 1.
A thin dielectric layer (“dielectric”) is disposed on the substrate above the channel, and a “gate” conductor (G) is disposed over the dielectric layer, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.)
Electrical connections (not shown) may be made to the source (S), the drain (D), and the gate (G). The substrate may be grounded or biased at a desired voltage depending on applications.
Generally, for NFET as an example, the drain (D) is biased positive and source (S) at ground, and when there is no voltage applied to the gate (G), there is no electrical conduction (connection) between the source (S) and the drain (D). As positive voltage is applied to the NFET gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain. This current flowing in the channel can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The FET 100 is exemplary of a MOSFET (metal oxide semiconductor FET) transistor. With the specified “n” and “p” types shown above, an “n-channel MOSFET” can be formed. With opposite polarities (swapping “p” for “n” in the diffusions, and “n” for “p” in the substrate or well), a p-channel FET can be formed. In CMOS (complementary metal oxide semiconductor), both n-channel and p-channel MOS transistors are used, often paired with one another.
While particular n- and p-type dopants are described herein according to NMOS technology, it is to be appreciated that one or more aspects of the present invention are equally applicable to forming a PMOS (generally, simply by reversing the n- and p-type dopants).
An integrated circuit (IC) device may comprise many millions of FETs on a single semiconductor “chip” (or “die”), measuring only a few centimeters on each side. Several chips may be formed simultaneously, on a single “wafer”, using conventional semiconductor fabrication processes including deposition, doping, photolithography, and etching.
Shallow Trench Isolation
FIG. 2A illustrates a FET 200, similar to the FET 100 shown in FIG. 1. In FIG. 2A, a well, in this case a p-well is shown. The source and drain diffusions are both n+, having a polarity which is opposite to that of the well, and the channel. In FIG. 2A, shallow trench isolation (STI) is shown, surrounding the FET (NFET).
To form STI, generally, a trench is etched into the substrate and filled with an insulating material such as oxide, to isolate one region of the substrate from an adjacent region of the substrate. One or more transistors (such as FETs) of a given polarity (NFET or PFET) may be disposed within a given area isolated by STI.
The shallow trench, as its name implies, for a given width is generally not as deep as a “deep trench”. For example, a deep trench may have a depth of approximately 2000-5000 nm (2-5 microns) and a width “W” of approximately 50-175 nm. Therefore, a deep trench is usually much deeper than it is wide, having an aspect ratio (depth-to-width) of approximately 40:1. Shallow trenches, such as are used for STI, may have a depth of approximately 20-300 nm and a width of at least 10 nm (they can generally be as wide as desired), resulting in an aspect ratio (depth-to-width) of approximately at most 3:1, more typically 2:1 or lower, such as 1:1.
Short Channel Effect, Halo and S/D Extension Implants
The reverse short-channel effect is a secondary effect describing the reduction in threshold voltage (Vt) in MOSFETs with non-uniformly doped channel regions as the gate length decreases. Since drive current is determined by Vt, shorter channel devices lose some driving ability. Reverse short channel effect (RSCE) is a result of non-uniform channel doping (halo doping) in modern processes. To combat drain-induced barrier lowering (DIBL), MOSFET channels are more doped near the source (S) and drain (D) terminals to reduce the size of the depletion region in the vicinity of these junctions (called halo doping to describe the limitation of this halo doping to the immediate vicinity of the junctions). At short channel lengths the halo doping of the source overlaps that of the drain, increasing the average channel doping concentration, and thus increasing the threshold voltage. This increased threshold voltage requires a larger gate voltage for channel inversion. However, as channel length is increased, the halo doped regions become separated and the doping mid-channel approaches a lower background level dictated by the body doping. This reduction in average channel doping concentration means Vt initially is reduced as channel length increases, but approaches a constant value independent of channel length for large enough lengths.
Ion implanting, in general is the process of introducing impurities such as dopants into the semiconductor substrate, or elements formed on the semiconductor substrate, and is often performed with a mask (or previously-formed elements in place) so that only certain areas of the substrate will be doped, or implanted. For example, doping is used to form the source and drain regions of an FET. An ion implanter is typically employed for the actual implantation.
Halo implants are well known as a means of moderating drain induced barrier lowing (DIBL) effects in very short MOSFETs. Conventionally, the halo implant is performed with the wafer tilted so that the implanted ions penetrate underneath the gate beyond the extent of the source/drain extension implant. The halo implant may be of the same polarity as the channel, and opposite polarity from the source/drain (S/D) implants.
Symmetric and asymmetric halo implants have been suggested to improve performance of low power short channel length field effect transistors (FET) by improving resistance to DIBL. Symmetric halo implants are pockets of increased dopant concentration of the same conductivity type as the channel region in areas adjacent to the FET source and drain edges. Each of these FET halo implants is doped opposite to the adjacent source/drain diffusion. Asymmetric halo implants extend normally adjacent to the drain but also they may extend differently adjacent the source than adjacent the drain. Halo implants may also extend into or under the channel region adjacent the source or drain edges. See U.S. Pat. No. 6,750,109 (IBM, 2004).
Source/Drain (S/D) “extension” implants are also well known. A S/D extension may be of the same polarity as the source/drain (S/D) implants, and opposite polarity from the channel. Generally, the S/D extension implants are located above (closer to the substrate surface) than the halo implants, and may extend from an inner edge of the respective source and drain diffusions. The extension doping areas overlap with gate conductor.
FIG. 2B illustrates a FET 220, similar to the FET 100 shown in FIG. 1. In FIG. 2B, the substrate (or cell well) and channel are p-type. The source and drain diffusions are both n-type (n+), having a polarity which is opposite to that of the well, and the channel, which is p-type.
In FIG. 2B, p+ halo implants are shown, as well as n+ extensions of the source/drain implants (or diffusions).
In FIG. 2B, sidewall spacers (“spacer”) are shown on sides of the gate stack (“gate”). Generally, the purpose of sidewall spacers is to control the location and extent of (by blocking) subsequent implants. For example, sidewall spacers disposed on opposite sides of a gate electrode structure cause subsequent implants to occur further away from the gate than otherwise (without the spacers in place), thereby controlling (increasing) the overlap length of a extension under the gate electrode structure.
Silicon nitride (Si3N4) and silicon oxide (SiO2) is a common spacer material. Spacers can be used for various purposes, such as controlling the location of halo implants, source/drain extensions and S/D diffusion.
Stress Layers, Electron and Hole Mobility
In some cases mechanical stress can be used advantageously to improve carrier mobility in a semiconductor device such as MOSFET (metal oxide semiconductor field effect transistor). For an NFET, tensile stress induced by a layer, such as epitaxial silicon-carbon (e-SiC) may cause the mobility of electrons to decrease. On the other hand, when the CMOS device being formed is a PFET, the compressive stress caused by the e-SiGe causes the mobility of the holes to increase.
Integration of Processes Features and Components
It is becoming increasingly difficult to integrate all of the necessary components (such as halo implants and source/drain extensions) to form the junction for the high performance CMOSFET by conventional ion implant followed by high temp thermal activation. Particularly, integration with epitaxial silicon-germanium (e-SiGe) is challenging. For example, the temperature required for e-SiGe process (500° C.-700° C.) may crystallize the amorphous Si formed by pre-amorphization implant (PAI), may diffuse the dopant by TED (Transient Enhanced Diffusion) and also may prevent the maximum activation by the high temp activation anneal such as laser anneal.
On the other hand, to preserve beneficial stress created by e-SiGe, PAI and high temperature anneal after e-SiGe formation is not a good process, because they create defects, particularly dislocations which relax the stress.
SOI Substrates
Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire.